1. Field of the Invention
This invention relates to a semiconductor device and more particularly to a semiconductor device in which any fault connection between chip electrodes and a wiring on a wiring substrate is prevented.
2. Description of the Related Art
There is currently known a semiconductor device called chip size package (hereinafter called the CSP) whose size is reduced almost to the size of a semiconductor chip.
The conventional CSPs are separated into a number of groups according to the kind of an intermediary for mounting the semiconductor chip. This intermediary is exemplified by a film carrier.
However, if the wiring on the film carrier and the chip electrodes on the semiconductor chip are interconnected by pressing under heat, such joint tends to be separated due to possible stresses so that the joint would become electrically opened.
FIG. 7 of the accompanying drawings of the present specification is a perspective view showing a conventional ordinary-type CSP.
As shown in FIG. 7, a semiconductor chip 1 is disposed on a TAB (Tape Automated Bonding) tape 2, which is a film carrier, has a size substantially equal to that of the TAB tape 2.
Aluminum (Al) chip electrodes (not shown) of the semiconductor chip 1 are electrically connected with bumps 9 via non-illustrated bumps in through-holes of the TAB tape 2. The whole of the semiconductor chip 1 is sealed by sealing resin 8 such as epoxy resin.
FIG. 8 is a fragmentary, enlarged cross-sectional view taken along line VIIIxe2x80x94VIII of FIG. 7.
In FIG. 8, the TAB tape 2 is composed of a polyimide tape 2b which is to be a base, and a wiring 2a of copper foil formed on the polyimide tape 2b, serving as a film carrier (a wiring substrate) on which the semiconductor chip 1 is to be supported.
The wiring 2a is prior formed on the polyimide tape 2b in a desired wiring pattern by vapor deposition of copper in the through-holes of the polyimide tape 2b. On the exposed surfaces of each bump 6, another bump 5 as of nickel (Ni) or gold (Au) is formed by plating.
The chip electrodes 4 are electrically connected with a wiring layer 3 in the semiconductor chip 1, the surface of which is covered with a chip covering film 12 so as to expose the chip electrodes 4.
The thus fabricated film carrier is used in assembling the semiconductor package as follows:
Firstly, with the bumps 5 aligned in confronting relationship with the chip electrodes 4, the wiring 2a are pressed against the bumps 6 under heat or ultrasonic waves using bonding tools. As a result, the individual bump 5 deforms to form gold-aluminum (Au.Al) alloy at the contact surface so that the bump 5 and the corresponding chip electrode 4 are pressed against each other under heat. Then the semiconductor chip 1 and chip covering film 12 are attached to each other by an adhesive material 11 to complete the semiconductor package. In the meantime, a solder resist 10 is applied over the surface of the exposed wiring 2a for corrosion-proofing.
However, according to this conventional technology, after the bump 5 and the chip electrode 4 are interconnected as pressed under heat, their joint tends to be separated due to possible stress as of the TAB tape 2, and as a result, the separated joint will be found as a fault connection during inspection after assembling of the semiconductor package.
With the foregoing problems in view, it is an object of this invention to provide a semiconductor device free of any connection fault between chip electrodes and bumps.
According to a first aspect of the invention, the above object is accomplished by a semiconductor device which comprises: a wiring substrate having a predetermined pattern of wiring formed on one surface; a semiconductor chip disposed on the other surface of the wiring substrate and having two or more chip electrodes in a common wiring layer; the wiring substrate having a number of through-holes; and a number of bumps formed respectively in the through-holes in conforming relationship with the chip electrodes and electrically connecting the wiring with the chip electrodes.
According to a second aspect of the invention, the above object is accomplished alternatively by a semiconductor device which comprises: a wiring substrate having a predetermined pattern of wiring formed on one surface; a semiconductor chip disposed on the one surface of the wiring substrate and having two or more chip electrodes in a common wiring layer; and a number of bumps disposed on the wiring respectively in conforming relationship with the chip electrodes and electrically connecting the wiring with the chip electrodes.
According to a third aspect of the invention, the above object is accomplished in another alternative way by a semiconductor device which comprises: a TAB (tape automated bonding) tape having a predetermined pattern of wiring formed on one surface; a semiconductor chip disposed on the other surface of the TAB tape and having two or more chip electrodes in a common wiring layer; the TAB tape having a number of through-holes; and a number of bumps formed respectively in the through-holes in conforming relationship with the chip electrodes and electrically connecting the wiring with the chip electrodes.
According to a fourth aspect of the invention, the above object is accomplished by still another alternative way by a semiconductor device which comprises: a TAB tape having a predetermined pattern of wiring formed on one surface; a semiconductor chip disposed on the one surface of the TAB tape and having two or more chip electrodes in a common wiring layer; and a number of bumps disposed on the wiring respectively in conforming relationship with the chip electrodes and electrically connecting the wiring with the chip electrodes.
In the semiconductor device of any one of the first through fourth aspects of the invention, as a preferred feature, the chip electrodes are arranged from an edge of the semiconductor chip toward its inner side.
As another preferred feature, the chip electrodes are arranged parallel to an edge of the semiconductor chip and the wiring is bent at at least one position.
As still another preferred feature, the chip electrodes are arranged parallel to an edge of the semiconductor chip and the wiring has an end width larger than an inter-electrode distance between the chip electrodes.
As a further preferred feature, the chip electrodes comprise at least one kind of terminals selected from ground, power-source and signal terminals of the semiconductor chip.
In the construction of the semiconductor device according to this invention, the device has at least two sets of chip terminals and bumps for a common wiring layer so that if the joint at one position happens to be separated, the remaining joints would be kept from being separated. Accordingly this semiconductor package is free of any connection fault.